1. Field of the Invention
The present invention generally relates to transmitting signals between different clock domains and, more specifically, to deterministic synchronization for transmitting signals between different clock domains.
2. Description of the Related Art
In many computer systems, signals that are passed from a first clock domain to a second clock domain are usually transmitted through a synchronization unit that resides between the two clock domains to ensure that no data is lost. However, conventional synchronization units have inherent non-deterministic behavior, meaning that a particular sequence of signal transitions passed multiple times from the first clock domain is not always output as a consistent sequence of transitions in the second clock domain. In other words, different sequences of signal transitions may occur in the second clock domain when the same sequence of signal transitions is applied in the first clock domain, such that a signal may transition one clock cycle earlier or later in the second due to variations in the resolution of metastable values. The non-deterministic behavior of the synchronization unit occurs because the flip-flops used in the synchronization unit may sample and resolve metastable values differently, even when the same sequence of transitions is passed between the two clock domains.
The non-deterministic behavior of the synchronization unit presents difficulties during functional debug of a device because applying same test stimulus multiple times in the first clock domain may produce inconsistent results in the second clock domain. Functional debug necessitates repeatability of a failure in order to successfully isolate, diagnose, and correct the circuitry causing the failure. With non-deterministic behavior, however, such repeatability is not guaranteed.
As the foregoing illustrates, what is needed in the art is a technique for deterministic synchronization of signals that are transmitted between different clock domains.